This research activity includes several research lines, focused on the use of RISC-V cores:
- Architectures for Artificial Intelligence (AI) and Machine Learning (ML)
In recent years, the rapid expansion of artificial intelligence and machine learning workloads has driven the adoption of increasingly specialized hardware accelerators capable of sustaining high computational throughput under tight energy constraints. Modern platforms integrate dedicated compute units, high‑bandwidth memory hierarchies, and dataflow‑optimized execution models tailored to deep neural networks. This research line focuses on the optimization of VLSI architectures for AI/ML processing, targeting both algorithmic refinements—aimed at reducing computational complexity and power consumption—and architectural enhancements designed to streamline memory organization, increase parallelism, and maximize overall throughput.
- Architectures for Post-Quantum Cryptography (PQC) and security
The transition toward quantum‑resistant security has accelerated the adoption of post‑quantum cryptographic schemes based on different techniques, including lattices, codes, multivariate constructions, and hash‑based primitives. Standardization efforts such as NIST’s PQC process are consolidating a new generation of algorithms that must be deployed across a wide spectrum of platforms, from constrained embedded devices to high‑performance network infrastructures. This research line focuses on the optimization of VLSI architectures for post‑quantum cryptographic accelerators, addressing both algorithmic transformations—aimed at reducing computational complexity, memory footprint, and energy consumption—and architectural enhancements designed to streamline polynomial arithmetic, improve memory organization, and maximize throughput while ensuring robustness against side‑channel and fault attacks.
Other topics related to this research activity are:
- Architectures for channel code decoders (turbo, LDPC, polar codes).
- Architectures for image and video compression