DEVELOPMENT OF NEW SIMULATION ALGORITHMS FOR TOPOLINANO SOFTWARE

ToPoliNano is a software developed at VLSI lab to easily design and simulate circuits with field coupled emerging technologies. It follows the traditional top-down methodology used in circuit design. The circuit to be studied is described with a structural VHDL netlist. The tool automatically generates the circuit’s layout. The obtained circuits can be simulated with an in-built simulation engine or exported on VHDL (using a RTL-level model of the technology) and simulated using HDL simulators. There is also an in-built graphical editor, MagCAD, that can be used to manually design circuits.

The objective of this thesis is to develop new simulation algorithms for ToPoliNano. These algorithms can be studied both for already supported technologies or for not yet supported technologies.

If interested please contact fabrizio.riente@polito.it.

 
DESIGN OF A 3D INTERFACE FOR MAGCAD GRAPHICAL EDITOR

ToPoliNano is a software developed at VLSI lab to easily design and simulate circuits with field coupled emerging technologies. It follows the traditional top-down methodology used in circuit design. The circuit to be studied is described with a structural VHDL netlist. The tool automatically generates the circuit’s layout. The obtained circuits can be simulated with an in-built simulation engine or exported on VHDL (using a RTL-level model of the technology) and simulated using HDL simulators. There is also an in-built graphical editor, MagCAD, that can be used to manually design circuits.

The objective of this thesis is to enhance the MagCAD graphical editor by introducing the support for new technologies. Many of this new technologies allows the design of 3D structures, so one of the goals of the thesis is to introduce a 3D interface in MagCAD for easy design of complex structures.

If interested please contact fabrizio.riente@polito.it.

 

DEVELOPMENT OF A SOFTWARE TOOL TO STUDY HIGHLY SCALED MOS DEVICES AND CIRCUITS

With the approaching of the end of MOSFET scaling, new transistors are developed to improve circuits performance. These new devices, like FinFET, Gate All Around FET and Tunnel FET, enable the overcoming some of the limitations of traditional FETs. To study these devices it is important to evaluate the performance of the device itself but also their impact at logic gate and system level. To reach this goal it is possible to use a tool developed at the VLSI lab, TAMTAMS.

The objective of this thesis is to design and develop a new version of TAMTAMS software, and it offers the unique possibility to improve both programming and electronic devices and systems knowledge. The first step of the work is to analyze the structure of current version of TAMTAMS. The second step involves the design of the core parts of the tool using JAVA language. The third part involves the development of advanced features in the new version of TAMTAMS.

If interested please write at marco.vacca@polito.it.