DEVELOPMENT OF A SIMULATION ENVIRONMENT FOR THE TOPOLINANO FRAMEWORK
ToPoliNano is a design framework developed at VLSI lab to easily design and simulate circuits with field coupled emerging technologies. It follows the traditional top-down methodology used in circuit design. The circuit to be studied is described with a structural VHDL netlist. The tool automatically generates the circuit’s layout. The obtained circuits can be simulated with an in-built simulation engine or exported on VHDL (using a RTL-level model of the technology) and simulated using HDL simulators. There is also an in-built graphical editor, MagCAD, that can be used to manually design circuits.
The objective of this thesis is to develop a simulation environment for ToPoliNano. These algorithms can be studied both for already supported technologies or for not yet supported technologies.
If interested please contact fabrizio.riente@polito.it, maurizio.zamboni@polito.it, mariagrazia.graziano@polito.it.
DEVELOPMENT OF A STANDARD CELL LIBRARY FOR THE TOPOLINANO SUPPORTED TECHNOLOGIES
ToPoliNano is a design framework developed at VLSI lab to easily design and simulate circuits with field coupled emerging technologies. It follows the traditional top-down methodology used in circuit design. The circuit to be studied is described with a structural VHDL netlist. The tool automatically generates the circuit’s layout. The obtained circuits can be simulated with an in-built simulation engine or exported on VHDL (using a RTL-level model of the technology) and simulated using HDL simulators. There is also an in-built graphical editor, MagCAD, that can be used to manually design circuits.
The objective of this thesis is to develop a standard cell library to enhance the MagCAD graphical editor. The developed standard cell libraries will be used to make architectural exploration of the involved technologies a compare them with state of art CMOS.
If interested please contact fabrizio.riente@polito.it, maurizio.zamboni@polito.it, mariagrazia.graziano@polito.it.
DEVELOPMENT OF A SOFTWARE TOOL TO STUDY HIGHLY SCALED MOS DEVICES AND CIRCUITS
With the approaching of the end of MOSFET scaling, new transistors are developed to improve circuits performance. These new devices, like FinFET, Gate All Around FET and Tunnel FET, enable the overcoming some of the limitations of traditional FETs. To study these devices it is important to evaluate the performance of the device itself but also their impact at logic gate and system level. To reach this goal it is possible to use a tool developed at the VLSI lab, TAMTAMS.
The objective of this thesis is to design and develop a new version of TAMTAMS software, and it offers the unique possibility to improve both programming and electronic devices and systems knowledge. The first step of the work is to analyze the structure of current version of TAMTAMS. The second step involves the design of the core parts of the tool using JAVA language. The third part involves the development of advanced features in the new version of TAMTAMS.
If interested please write at marco.vacca@polito.it.