PHYSICAL ANALYSIS OF RACETRACK LOGIC STRUCTURES

Racetrack memories are a new type of magnetic memories developed by IBM laboratories. They can be seen as the implementation at nanoscale of the old tape memories. They allow designing 3D memories with very high bit density. The racetrack logic concept is a modification of a racetrack memory to enable logic-in-memory computation. Elementary logic operations are possible, so the memory acts both as a logic and memory device.

The objective of this thesis is to analyze at physical level the racetrack logic devices. As a first step, physical level simulations will be employed to validate the structure behavior. A second objective of the thesis is to design new innovative structures based on the racetrack logic concept. Finally high-level models, enhanced by information obtained from physical simulation, will be developed to allow the simulation of complex structures.

If interested please write at mariagrazia.graziano@polito.it or fabrizio.riente@polito.it.

 

RACETRACK LOGIC CIRCUIT ANALYSIS AND DESIGN

Racetrack memories are a new type of magnetic memories developed by IBM laboratories. They can be seen as the implementation at nanoscale of the old tape memories. They allow designing 3D memories with very high bit density. The racetrack logic concept is a modification of a racetrack memory to enable logic-in-memory computation. Elementary logic operations are possible, so the memory acts both as a logic and memory device. Each element behaves as a complex majority logic gate coupled to a shift register. From the logic point of view, a racetrack logic element can behave both as a combinational and sequential circuit, opening up new ways of designing logic circuits.

The objective of this thesis is to design and simulate logic circuits based on the racetrack logic elements. First high-level models of the technology must be developed. Then, a theoretical analysis of circuits that can exploit the unique features of the technology will be necessary. Finally, circuits will be simulated to validate them and understand their performance.

If interested please write at mariagrazia.graziano@polito.it or fabrizio.riente@polito.it.

 

DESIGN OF  A FULLY INTEGRATED ON-CHIP COIL FOR CLOCKING pNML CIRCUITS

Perpendicular NanoMagnet Logic (pNML) is an emerging technology that intrinsically enables the design of 3D circuits. Given that one of the main limitations is the efficient generation of the out-of-plane field.

The objective of this thesis is the design and simulate a fully integrated and efficient on-chip coil for clocking pNML circuits.

If interested please contact mariagrazia.graziano@polito.it or fabrizio.riente@polito.it.

 

DESIGN OF CONVOLUTIONAL NEURAL NETWORKS USING pNML TECHNOLOGY

Perpendicular NanoMagnet Logic (pNML) is an emerging technology that intrinsically allows to design 3D circuits. Given that one of the main limitations of implementing convolutional neural networks in CMOS is the impossibility to have 3D circuits, pNML technology is the ideal candidate for this kind of circuits.

The objective of this thesis is the design and simulation of a simple multilayer convolutional neural network on pNML technology.

If interested please contact mariagrazia.graziano@polito.it or giovanna.turvani@polito.it.

 

DESIGN OF LOGIC-IN-MEMORY CIRCUITS

Logic-in-memory or in-memory computing is a new computational paradigm where logic and memory are no more two separated entities but are merged in one single circuit. This new paradigm is interesting because it can break the “memory wall”, which is currently one of the major bottlenecks of modern computational systems. Logic-in-memory circuits can be designed using standard MOS technology, using the possibilities offered by 3D technology or by employing emerging technologies.

The aim of this thesis is to design innovative logic-in-memory circuits based on MOS technology. Circuits can be built exploiting one layer or multilayer circuits. Innovative circuits structures, where the placement of each logic and memory block and their interaction is detailed studied, must be designed.

If interested please contact maurizio.zamboni@polito.it or giovanna.turvani@polito.it 

 
DESIGN OF LOGIC-IN-MEMORY CIRCUITS WITH EMERGING TECHNOLOGIES

Logic-in-memory or in-memory computing is a new computational paradigm where logic and memory are no more two separated entities but are merged in one single circuit. This new paradigm is interesting because it can break the “memory wall”, which is currently one of the major bottlenecks of modern computational systems. Logic-in-memory circuits can be designed using standard MOS technology, using the possibilities offered by 3D technology or by employing emerging technologies.

The aim of this thesis is to design innovative logic-in-memory circuits using emerging technologies. Circuits can be built exploiting one layer or multilayer circuits. The aim is to study architectures based entirely on emerging technologies or where the emerging technologies are mixed with standard MOS devices.

If interested please contact maurizio.zamboni@polito.it or giovanna.turvani@polito.it.