This research activity includes several research lines, namely:

  • Architectures for channel code decoders (turbo, LDPC, polar codes).

In the last years, both wireless and wired communication standards have included powerful error correcting codes at the physical layer. The 5G seems to continue this direction including also recently-invented codes, such as Polar Codes. This research line aims at investigating optimization of VLSI architectures for channel code decoders. The optimization can be either at an algorithmic level to achieve complexity and/or power consumption reduction or at architectural level to reduce/simplify the memory structure and to increase the throughput.

  • Architectures for Multiple-Input-Multiple-Output (MIMO) receivers.

MIMO receivers feature a very high complexity, especially when large-scale antenna systems (massive-MIMO) are involved. This research line aims to study high throughput VLSI architectures by trying to optimize several metrics, mainly throughput, complexity, and flexibility.

  • Architectures for Ultra-Wide-Band (UWB) systems

Impulse Radio UWB (IR-UWB) is a very interesting technology able to achieve effective communications with very low complexity circuits. This technology seems particularly suited for short-range communications such as body area networks. Thus, this research line aims to study circuits, architectures, and applications for IR-UWB transmission and reception.

  • Architectures for image and video compression

The High-Efficiency Video Coding (HEVC) standard is gaining large popularity as it will be part of the second generation of digital video broadcasting systems. HEVC features a significant performance increase with respect to H.264/AVC at the expense of a large computational complexity. This research line aims to investigate VLSI architectures able to implement in an optimized way the most demanding tasks of image and video compression systems, including the ones in HEVC.

  • Architectures for Event-Based processing

Continuous-time signal processing has gained in the last years the attention of several researchers as it can be applied to several contexts including robotic, bio and neuro inspired applications. This research line focuses mainly on neuromorphic and quasi-digital signal representation and processing. It aims to develop optimized digital systems able to perform even complex tasks with a very limited power consumption.


  • Innovative architectures for digital signal processing.

Today, Digital Signal Processing (DSP) is pervasive and it includes several architectures, systems, and applications. This research line aims to study the effect of innovative DSP techniques on specific applications, namely the use of approximate computing and/or speculative arithmetic applied to video compression, channel code decoding, …