APPLICATION SPECIFIC APPROXIMATE COMPUTING

Several applications are intrinsically resilient to arithmetic errors. As a consequence, they are ideal candidates for the approximate computing paradigm.

The objective of this thesis is to investigate the effect of approximate computing in real applications, where the amount of computational complexity is relevant. For such applications simulating the effect of approximate computing with a software model is not always possible. Thus, we are developing an FPGA-based framework where part of the system runs as software on an ARM processor equipped with Linux, wheres the approximations are part of a custom peripheral connected to the ARM processor. This approach allows to reproduce the real system behavior, instead of performing simulations.

If interested please write at maurizio.martina@polito.it or guido.masera@polito.it

 

VLSI ARCHITECTURES FOR VIDEO CODING

Video coding is a very computationally intensive application requiring optimized accelerators. Achieving such accelerators means working both at algorithmic and architectural level in order to save area and power consumption while improving the speed and throughput.

The objective of this thesis is to analyze one or more blocks involved in video coding and propose a new and effective architecture. As a first step, a high level software model will be employed to understand the details of the operations and, if needed, to modify the algorithms. Then, the architecture will be developed and validated with the required CAD tools.

If interested please write at maurizio.martina@polito.it or guido.masera@polito.it.

 

VLSI ARCHITECTURES FOR 5G COMMUNICATIONS

The new standards for wireless communications (5G communications) are focusing on several aspects requiring notheworthy computational complexity. Moreover, the increasing requirements in terms of  throughput and latency impose to rely on optimized VLSI architectures. One of the most interesting aspects in this scenario is the physical layer, where Error Correcting Codes (ECC) are used.

The objective of this thesis is to investigate algorithms and architectures for 5G communications critical blocks, such as the new Polar Codes. Starting from a high-level model of the system, one or more algorithmic/architectural solutions will be analyzed and implemented. Then, thanks to EDA tools these solutions will be verified and validated.

If interested please write at maurizio.martina@polito.it or guido.masera@polito.it.

 

VLSI ARCHITECTURES FOR EVENT-BASED PROCESSING

Several applications, especially in the field of robotics and bio-inspired processing, can take advantage of the event-based representation, where the information is coded as the distance between spikes, rather than with ‘traditional’ samples. This approach allows to significantly reduce the complexity and the power consumptionof several processing systems.

The objective of this thesis is to investigate, in collaboration with the Italian Institute of Technology (IIT), system and architectures for event-based processing.

If interested please write at maurizio.martina@polito.it or guido.masera@polito.it or danilo.demarchi@polito.it or paolo.mottoros@iit.it.